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Logic Analyzer (Option R&S RTB-B1, MSO)
R&S
®
RTB2000
226User Manual 1333.1611.02 ─ 03
BUS<b>:CPARallel:CLOCk:SOURce on page 439
BUS<b>:CPARallel:CS:SOURce on page 439
Set to Default
Resets the data lines of the parallel bus to the default order D0...D15.
Chip Select
Enables the chip select line for the parallel clocked bus.
Remote command:
BUS<b>:CPARallel:CS:ENABle on page 439
Polarity
For the parallel clocked bus, selects if the chip select signal is high active (
high =
1) or low active (
low = 1).
Remote command:
BUS<b>:CPARallel:CS:POLarity on page 440
Slope
For the parallel clocked bus, selects if the data is sampled on the rising (
) or falling
(
) slope of the clock, or on both edges ( ) of a double data rate clock. The clock
slope marks the begin of a new bit.
Remote command:
BUS<b>:CPARallel:CLOCK:SLOPe on page 439
13.5.2 Decode Results
When the configuration of the parallel bus is complete, the signal can be decoded:
1. In the "Bus" menu, enable "Decode".
2. In the "Display" menu, select the result display settings.
See Chapter 12.1.2, "Display Settings", on page 167.
3. In the "Bus Table" menu, enable the "Bus Table". Adjust the table settings.
See also: Chapter 12.1.3, "Bus Table: Decode Results", on page 167
Parallel Buses
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