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Network operation and remote control
R&S
®
MXO 4 Series
391User Manual 1335.5337.02 ─ 05
Table 16-2: Meaning of the bits used in the status byte
Bit No. Meaning
0...1 Not used
2 Error Queue not empty
The bit is set when an entry is made in the error queue. If this bit is enabled by the SRE, each
entry of the error queue generates a service request. Thus an error can be recognized and
specified in greater detail by polling the error queue. The poll provides an informative error mes-
sage. This procedure is to be recommended since it considerably reduces the problems
involved with remote control.
3 QUEStionable status register summary bit
The bit is set if an EVENt bit is set in the QUEStionable status register and the associated
ENABle bit is set to 1. A set bit indicates a questionable instrument status, which can be speci-
fied in greater detail by querying the STATus:QUEStionable status register.
4 MAV bit (message available)
The bit is set if a message is available in the output queue which can be read. This bit can be
used to enable data to be automatically read from the instrument to the controller.
5 ESB bit
Sum bit of the event status register. It is set if one of the bits in the event status register is set
and enabled in the event status enable register. Setting of this bit indicates a serious error which
can be specified in greater detail by polling the event status register.
6 MSS bit (main status summary bit)
The bit is set if the instrument triggers a service request. This is the case if one of the other bits
of this registers is set together with its mask bit in the service request enable register SRE.
7 STATus:OPERation status register summary bit
The bit is set if an EVENt bit is set in the OPERation status register and the associated
ENABle bit is set to 1. A set bit indicates that the instrument is just performing an action. The
type of action can be determined by querying the STATus:OPERation status register.
16.5.3.2 Event status register (ESR) and event status enable register (ESE)
The ESR is defined in IEEE 488.2. It can be compared with the EVENt part of a SCPI
register. The event status register can be read out using command *ESR?.
The ESE corresponds to the ENABle part of a SCPI register. If a bit is set in the ESE
and the associated bit in the ESR changes from 0 to 1, the ESB bit in the STB is set.
The ESE register can be set using the command *ESE and read using the command
*ESE?.
Table 16-3: Meaning of the bits used in the event status register
Bit No. Meaning
0 Operation Complete
This bit is set on receipt of the command *OPC exactly when all previous commands have been
executed.
1 Not used
Remote control - status reporting system
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