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Figure 7.1 Measurement Schematic Diagram of Phase Deviation ......................... 66
Figure 7.2 Waveforms before Averaging .........................................................................69
Figure 7.3 Waveforms after 128 Times of Averaging ..................................................69
Figure 7.4 Memory Depth .................................................................................................... 73
Figure 8.1 Schematic Diagram of the Acquisition Memory ......................................78
Figure 8.2 Schematic Diagram of Trigger Holdoff ........................................................81
Figure 8.3 Positive Pulse Width/Negative Pulse Width ..............................................83
Figure 8.4 Positive Slope Time/Negative Slope Time ................................................. 86
Figure 8.5 Pattern Trigger ..................................................................................................... 92
Figure 8.6 Virtual Keypad for Pattern Setting ................................................................93
Figure 8.7 Duration Trigger .................................................................................................. 95
Figure 8.8 Timeout Trigger ................................................................................................... 97
Figure 8.9 Runt Trigger .......................................................................................................... 99
Figure 8.10 Delay Trigger ....................................................................................................104
Figure 8.11 Setup/Hold Trigger ........................................................................................106
Figure 8.12 Nth Edge Trigger ............................................................................................ 108
Figure 8.13 Schematic Diagram of RS232 Protocol ...................................................110
Figure 8.14 Schematic Diagram of I2C Protocol .........................................................112
Figure 8.15 Virtual Keypad for Binary Data Bit ........................................................... 114
Figure 8.16 Virtual Keypad for Hex Data Bit ................................................................115
Figure 8.17 Sequential Chart of SPI Bus ........................................................................116
Figure 8.18 Data Frame Format of the CAN Bus ........................................................ 118
Figure 8.19 Sample Position ..............................................................................................120
Figure 8.20 Frame Format of FlexRay Bus .................................................................... 121
Figure 8.21 Data Frame Format of the LIN Bus .......................................................... 124
Figure 8.22 Sample Position ..............................................................................................126
Figure 8.23 Sequential Chart of I2S Bus ........................................................................127
Figure 8.24 Formats of the Command Word, Data Word, and Status Word of
the 1553B Bus ....................................................................................................................
130
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XI
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