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SDS6000L User Manual
int. s i g l e n t . c o m 77
The 2x interpolation implemented is a classic sinx/x up-sampling processed by a high-speed Field
Programmable Gate Array (FPGA) in real-time. The following figure shows the frequency response of
the Finite Impulse Response (FIR) digital filter used in the interpolation. From the frequency response,
we can see it has no attenuation at fmax = 2 GHz, and ~70 dB attenuation at 5 GHz – fmax = 3 GHz,
which provides enough alias suppression for signals in the operating bandwidth. The aliasing
associated with signals above 2 GHz is minimized by the fast roll-off of the analog front end.
Higher measurement precision
The ADC sample rate to bandwidth ratio in the SDS6000L is 2.5:1. That means for a 2 GHz input there
are 2.5 samples/period. Without any extra interpolation, the measurements on vertical waveform
elements such as Maximum, Minimum, and Peak-peak will introduce considerable error at high-
frequency input. The figure below shows an example in which a 500 MHz signal is sampled at 5 GSa/s:
Error on vertical measurement introduced by insufficient sampling
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