Rohde & Schwarz NGM-COM2B Rohde &Schwarz power supply bundle

User manual NGM COM2a - Page 188

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Additional Basics on Remote Control
R&S
®
NGL200/NGM200
186User Manual 1178.8736.02 ─ 09
A.2.1 Preventing Overlapping Execution
Table A-5: Synchronization using *OPC, *OPC? and *WAI
Command Action Programming the controller
*OPC
Sets the Operation Complete bit
in the ESR after all previous com-
mands have been executed.
Setting bit 0 in the ESE
Setting bit 5 in the SRE
Waiting for service request
(SRQ)
*OPC?
Stops command processing until
1 is returned. It occurs after the
Operation Complete bit has been
set in the ESR. This bit indicates
that the previous setting has been
completed.
Sending *OPC? directly after the
command whose processing
should be terminated before other
commands can be executed.
*WAI
Stops further command process-
ing until all commands have been
executed before *WAI.
Sending *WAI directly after the
command whose processing
should be terminated before other
commands are executed
To prevent an overlapping execution of commands the commands *OPC, *OPC? or
*WAI can be used. All three commands cause a certain action only to be carried out
after the hardware has been set. The controller can be forced to wait for the corre-
sponding action.
The R&S NGL/NGM series does not support parallel processing of remote commands.
If OPC? returns a "1", the device is able to process new commands.
A.3 Status Reporting System
The status reporting system stores all information on the current operating state of the
instrument and errors which have occurred. This information is stored in the status reg-
isters and in the error queue. You can query both via RS-232, USB, GPIB or LAN inter-
face (STATus... commands).
A.3.1 Structure of a SCPI Status Register
Each standard SCPI register consists of 2 or 3 parts (Event, Condition and Enable reg-
ister). Each part has a width of 16 bits and has different functions. The individual bits
are independent of each other, i.e. each hardware status is assigned a bit number
which is valid for all 2 or 3 parts. Bit 15 (the most significant bit) is set to zero for all
parts. Thus the controller can process contents of the register parts as positive inte-
gers.
STATus:QUEStionable:INSTrument:ISUMmary1 exists as often as device chan-
nels are available (e.g. NGL201 = 2 channels = 2 status register). Accordingly, the
description text of the channel information changes in
Figure A-1 (e.g. instrument 1 =
channel 1, instrument 2 = channel 2 etc.).
Status Reporting System
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