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Remote Operation
Checking 525B Status
4
4-23
Serial Poll Status Byte (STB)
The Calibrator sends the serial poll status byte (STB) when it responds to a serial
poll. This byte is cleared (set to 0) when the power is turned on. The STB byte is
defined as shown in Figure 4-6. Refer to the *STB? Command for RS-232
interface operation in Chapter 5 for more information.
76543210
0
RQS
MSS
ESB MAV EAV 0
0
0
Requesting service. The RQS bit is set to 1 whenever bits ESB, MAV, EAV, or ISCB
change from 0 to 1 and are enabled (1) in the SRE. When RQS is 1, the 525A asserts
the SRQ control line on the IEEE-488 interface. You can do a serial poll to read this bit
to see if the 525B is the source of an SRQ.
Master summary status. Set to 1 whenever bits ESB, MAV, EAV, or ISCB are 1 and
enabled (1) in the SRE. This bit can be read using the *STB? command in serial
remote control in place of doing a serial poll.
Set to 1 when one or more ESR bits are 1.
Message available. The MAV bit is set to 1 whenever data is available in the 525B’s
IEEE-488 interface output buffer.
Error available. An error has occurred and an error is available to be read from the
error queue by using the FAULT? query.
RQS
MSS
ESB
MAV
EAV
fcn18f.eps
Figure 4-6. Serial Poll Status Byte (STB) and Service Request Enable (SRE)
Service Request (SRQ) Line
IEEE-488 Service Request (SRQ) is an IEEE-488.1 bus control line that the
Calibrator asserts to notify the controller that it requires some type of service.
Many instruments can be on the bus, but they all share a single SRQ line. To
determine which instrument set SRQ, the Controller normally does a serial poll of
each instrument. The calibrator asserts SRQ whenever the RQS bit in its Serial
Poll Status Byte is 1. This bit informs the controller that the Calibrator was the
source of the SRQ.
The Calibrator clears SRQ and RQS whenever the controller/host performs a serial
poll, sends *CLS, or whenever the MSS bit is cleared. The MSS bit is cleared only
when ESB and MAV are 0, or they are disabled by their associated enable bits in
the SRE register being set to 0.
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