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Chapter 18 Store and Load RIGOL
MSO7000/DS7000 User Guide 18-25
Threshold
0 V
Rx
OFF
Polarity
Endian
LSB
Data
8 bits
Stop Bit
1 bit
Parity
None
Package
OFF
Separator
0(NUL)
I2C
Bus Status
OFF
Clock
CH1
SCL Thre
0 V
SDA
CH2
SDA Thre
0 V
Exchange
SCL/SDA
R/W
Without
SPI
Bus Status
OFF
Mode
Timeout
Timeout
1 μs
CLK
CH1
Threshold
0 V
Slope
Rising
MISO
CH2
Threshold
0 V
MOSI
OFF
Polarity
Width
8
Endian
MSB
LIN
Bus Status
OFF
Source
CH1
Threshold
0 V
Baud
19.2 kbps
Parity
Without
Version
Both
CAN
Bus Status
OFF
Source
CH1
Threshold
0 V
Signal
CAN_L
Baud
1 Mbps
Sample Position
50%
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