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Chapter 11 Protocol Decoding RIGOL
MSO7000/DS7000 User's Guide 11-3
Falling : samples the channel data on the falling edge of the clock.
Both
: samples the channel data on both the rising edge and the
falling edge of the clock.
Set the threshold
When the clock signal is an analog channel (CH1-CH4), you need to set a
threshold. Press Threshold, rotate the multifunction knob or use the
pop-up numeric keypad to set the threshold.
Set the clock compensation
Press CLK Tune, rotate the multifunction knob or use the pop-up
numeric keypad to set the compensation time. You can fine-tune the phase
deviation between the clock line and data line. The available range is from
-100 ms to 100 ms. The negative value indicates that the clock moves
ahead, and the positive value indicates that the clock moves behind.
3
． Bus setting
Press Bus to enter the bus setting menu.
Set the bus
Press BUS to select the digital bus for Parallel decoding, as shown in the
following table.
Bus
Width
Bit X
Channel
Remarks
CH1
1
0
CH1
Width, Bit X, and CH are set
automatically, and you cannot
modify them.
CH2
1
0
CH2
Width, Bit X, and CH are set
automatically, and you cannot
modify them.
CH3
1
0
CH3
Width, Bit X, and CH are set
automatically, and you cannot
modify them.
CH4
1
0
CH4
Width, Bit X, and CH are set
automatically, and you cannot
modify them.
D7-D0
8
0 (default)
D0
(default)
Bit0 to Bit7 are set to D0 to D7
respectively. Width is set
automatically, and you cannot
modify them.
D15-D8
8
0 (default)
D8
(default)
Bit0 to Bit7 are set to D8 to D15
respectively. Width is set
automatically, and you cannot
modify them.
D15-D0
16
0 (default)
D0
Bit0 to Bit15 are set to D0 to
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