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SIGLENT
SDS2000X User Manual 89
CS
High voltage level of CS signal is available
CLK Timeout
If the time between two edges of clock signal is less than (or
equal to) the value of timeout, the signal between the two edges
is treated as a frame. The range of clock timeout is 100ns-5ms.
9. Press the Bit Order softkey to select the bit order (LSB or MSB).
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