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RIGOL Chapter 8 Protocol Decoding
8-2 MSO2000A/DS2000A User’s Guide
Parallel Decoding
Parallel bus consists of clock line and data line. As shown in the figure below, CLK is
the clock line, while Bit0 and Bit1 are the 0 bit and 1st bit on the data line respectively.
The oscilloscope will sample the channel data on the rising edge, falling edge or the
rising/ falling edge of the clock and judge each data point (logic “1” or logic “0”)
according to the preset threshold level.
Figure 8-1 Parallel Decoding
Press Decode1 Decode to select “Parallel” and open the parallel decoding
function menu.
1. Clock Line Setting ( CLK)
Press CLKChannel to select any channel (CH1, CH2 or any channel of D0-D15)
as the clock channel. If “None” is selected, no clock channel is set.
Press Slope to set the oscilloscope to sample the channel data on the rising
edge (
), falling edge ( ) or rising/ falling edges ( ). If no clock
channel is selected, the instrument will sample when the channel data jumps
during the decoding.
2. Data Line Setting
Set the bus bits
Press Bus Bits to set the data width of the parallel bus namely the number
of bits per frame. The default is 8 and the maximum is 18 bits (Bit0,
Bit1…Bit17).
Specify data channel for each bit.
First, press CurrentBit to select the bit that needs to specify channel. The
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