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SDS6000A Series Digital Oscilloscope User Manual
int.siglent.com 153
Connect the data, CLK, and ~CS signals of an SPI bus respectively to C1, C2,
and C3. Data width = 8-bit, Bit order = MSB, CS polarity = active low, and 12
data bytes are transmitted in one frame.
In the SPI trigger signal menu, set the source and threshold of CLK, MISO, and
CS signals, then copy the trigger settings to decoding. Adjust the timebase, so
that there is a falling edge on the CS signal shown on the screen:
When the CS type is set to Clock Timeout, turn on Cursor, measure the clock
idle time between frames as 150 us, and measure the interval between clock
pulses as 1.28 us, then set the timeout to a value between 1.28 us and 150 us.
In this example it is set to 5 us:
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