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Appendices
Warning and Error Messages B
B-3
145 Selected mode is not available when phase lock master or slave
146 Cannot delete arbs while a sequence is running
147 Current set-up requires an arb wfm which does not exist
148 Trig/gate mode and seq step value cause a trigger conflict
149 Seq step value can't mix edge and level between segments
150 Number of pulses in train must be between 1 and 10
151 Pulse train base level must be >-5.0 V and <+5.0 V
152 Pulse level must be >-5.0 V and <+5.0 V
153 Pulse number must be between 1 and 10
154 Sweep frequency values must be 0.001 mHz to 16 MHz
155 Sweep start freq must be less than stop freq
156 Sweep stop freq must be greater than start freq
157 Sweep time value is out of range 0.03 s < n < 99 9s
158 Sweep marker value is out of range 0.001 Hz < n < 16 MHz
160 Not locked. This error indicates that a phase locking operation has failed.
161 Illegal phase value
178 SUM ratio is not possible within level constraints
179 SUM and internal MOD cannot be active together
180 Modulation depth or SCM level is out of range
182 This channel’s waveform ram is full
184 SUM or Modulation conflict
186 Inter channel lock not possible. Lock status is off.
This error may occur for several reasons. In each case there is a conflict of the
phase locking settings. In
most cases the status of the phase lock is set to off.
Any of the following conditions will cause this error:
1. More than one master channel is enabled.
2. No master channel is enabled.
3. The locked channels contain a m
ixture of DDS and PLL generated
waveforms.
4. Frequency tracking is enabled (mode:
master/freq) but the frequencies are
not the same on all channels. If PLL waveforms are locked the mode will be
forced to frequency tracking.
5. A locked channel is not set to continuous mode.
6. An attempt is made to turn on phase lock with a frequency set too high. Note
that the maxim
um frequency for phase locked DDS operation is 10 MHz.
7. An attempt is made to set the frequency
too high during phase lock. This
error does not set phase lock to off, the system simply inhibits the setting of
the incorrect frequency.
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