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SDG7000A User Manual
WWW.SIGLENT.COM 61 /
133
Resampling
4X
Resampling
4X
D/A
D/A
I Data
RAM
Q Data
RAM
250Sa/s
~1.25GSa/s
1.25GSa/s
5GSa/s
Iout
Qout
IQ Data Flow
Figure 9.4 Baseband I/Q mode
Resampling
4X
Resampling
4X
Digital
Quadrature
Modulator
D/A
I Data
RAM
Q Data
RAM
250Sa/s
~1.25GSa/s
1.25GSa/s 5GSa/s
Sout
IF Data Flow
Figure 9.5 IF mode
The schematic block diagram of the internal quadrature modulator is shown in the figure below:
I(nT)
s(nT)
cos(ω
c
nT)
0°
90°
Q(nT)
sin(ω
c
nT)
-
+
Figure 9.6 Schematic block diagram of quadrature modulator
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