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52
Bit Definitions - Standard Event Register
Bit
Decimal
Val ue
Definition
0 OPC 1
Operation Complete. All commands prior to and
including an *OPC command have been executed.
1 Not Used 0 Always set to 0.
2 QYE 4
Query Error. The power supply tried to read the
output buffer but it was empty. Or, new command
line was received before a previous query had been
read. Or, both the input and output buffers are full.
3 DDE 8
Device Error. A self-test or calibration error
occurred.
4 EXE 16 Execution Error. An execution error occurred.
5 CME 32
Command Error. A command syntax error
occurred.
6 Not Used 0 Always set to 0.
7 PON 128
Power On. Power has been turned off and on since
the last time the event register was read or cleared.
The standard event register is cleared when:
1. You execute the *CLS (clear status) command.
2. You query the event register using the *ESR? (Event Status register) command.
For example, if 28 (4 + 8 + 16) is returned when you query the status of the standard
event register, it is convinced that QYE, DDE, and EXE conditions have occurred.
The standard event enable register is cleared when:
1. You execute the *ESE 0 command.
2. You turn on the power and have configured the power supply using the *PSC 1
command.
3. The enable register will not be cleared at power-on if you have configured the
power supply with the *PSC 0 command.
For example, you must send *ESE 24 (8 + 16) to enable DDE and EXE bits.
The Status Byte Register
The status byte summary register reports conditions from the other status registers.
Query data that is waiting in the power supply’s output buffer is immediately reported
through the “Message Available” bit (bit 4) of status byte register. Bits in the
summary register are not latched. Clearing an event register will clear the
corresponding bits in the status byte summary register. Reading all messages in the
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