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SDG7000A User Manual
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133
As we can see from the table above, the frequency errors introduced on both channels are small,
but not proportional, which results in the two frequencies that were integer multiples no longer
being integer multiples, with the result that they are not phase-locked. The following is the phase
drift (approximately 6.9 ns) observed in this example after 17.3 hours for both channels in
“Independent” mode.
In “Lock” mode, the unit forces the higher frequency FTW to be an integer multiple of the lower
frequency FTW for frequencies that are an integer multiple of each other, which may increase
the output error at the higher frequency but ensures phase lock between the two. In this example,
the outputs of the two channels in "Locked" mode are observed over a long period. As we can
see, the phases are always aligned.
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